Current mobile systems suffer from power leakage and consumption of semiconductor circuits. Moreover, current low-power circuits are based on conventional design schemes. However, mobile multi-core processor (MCP) implementations require a fundamentally different design approach for cores and on-chip memories. Still yet, current memory approaches are based on standard-based fixed speed having a fixed power supply. In some implementations, a sleep mode may be present. However, the sleep mode may take an extensive period of time for the memory to transition between sleep and wake modes.
U.S. Pat. No. 8,054,663 discloses a multi-memory chip memory configuration that utilizes a reference signal during use to measure process variation between memory segments and to compensate for the variation.
U.S. Pat. No. 7,873,775 discloses a multiple processor and memory segment device that utilizes a first primary set of memory segments and a secondary set of memory devices that are accessible through a memory segment of the primary set.
U.S. Pat. No. 7,772,880 discloses an intelligent multiple memory SoC design that is reconfigurable to process multiple application problems.
U.S. Pat. No. 7,715,255 discloses a multi-memory segment chip that utilizes the disablement or reprogramming of particular memory die after packaging.
U.S. Pat. No. 7,495,966 discloses a method for adjusting the “cycle voltage” of a memory block based upon the frequency of process cycles for that memory block.
U.S. Pat. No. 8,042,082 discloses a multi-memory segment stacked SOC device.
U.S. Pat. No. 7,913,000 discloses a multi-memory segment electronic device that utilizes a buffer for read operations.
U.S. Pat. No. 7,738,304 discloses a method for creating memory arrays with a mix of volatile and non-volatile memory segments.
U.S. Patent Application No. 2003/0161196 discloses a multi-component memory system that is mounted on a PCB with each memory segment having a branch point on the system bus.
U.S. Patent Application No. 2012/0004011 discloses a method for using both non-volatile and volatile memory in a mobile electronic device.
Unfortunately, none of these approaches addresses the deficiencies in the related art.